Technical Report: Designing High-Performance Real-Time SDRAM Controllers for Many-Core Systems (Revision 1.0)
Open-row real-time SDRAM controllers have been recently pinpointed as an interesting approach to effectively exploit wide SDRAM data buses often present in many-core platforms. However, their evaluation has mostly targeted specific DDR-generations. This is problematic, as every new DDR-generation introduces new architectural features and/or timing constraints. In this article, we address such challenge. More specifically, we propose a multi-generation open-row real-time SDRAM controller architecture. Furthermore, we examine the trends in terms of worst-case latency over modules from DDR2, DDR3 and DDR4 SDRAMs.
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